Memory device with latch-based neural network weight parity detection and trimming
US12061542B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2022 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | Jun 22, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Latch-based methods and apparatus for performing neural network weight parity detection on the die of a non-volatile memory (NVM) array to detect bit flip errors within neural network weight data are described, particularly for use with floating point number values. Upon detection of a parity error in a neural network weight, the erroneous weight is set to zero to trim the corresponding neuron from the network, thus preventing the erroneous value from significantly affecting the network, particularly in situations where the bit flip would otherwise affect the magnitude of a floating-point weight value. The exemplary latch-based procedures described herein are linear procedures that do not require logic decisions. Procedures are also described that assess an amount of degradation in the NVM array based on parity bit data collected in the latches. Multiple plane and multiple die NVM array implementations are also described for massive parallel processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.