Multiple (multi-) die integrated circuit (IC) packages for supporting higher connection density, and related fabrication methods
US12062648B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2021 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | Jul 20, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15321
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Multiple (multi-) die integrated circuit (IC) packages for supporting higher connection density, and related fabrication methods. The multi-die IC package includes split dies that provided in respective die packages that are stacked on top of each other to conserve package area. To support signal routing, including through-package signal routing that extends through the die package, each die package includes vertical interconnects disposed adjacent to their respective dies and coupled to a respective package substrate (and interposer substrate if provided) in the package substrate. In this manner, as an example, through-silicon-vias (TSVs) are not required to be fabricated in the multi-die IC package that extend through the dies themselves to provide signal routing between the respective die packages. In another example, space created between adjacent interposer substrates of stacked die packages, as stood off from each other through the interconnect bumps, provides an area for heat dissipation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.