Cooling in conductors for chips
US12063763B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2021 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | Oct 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K7/20927
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system for cooling a power component includes a first metal layer. A cooling layer having a first surface is in contact with a surface of the first metal layer. A second metal layer is included having a surface in contact with a second surface of the cooling layer opposite the first metal layer. The cooling layer is of a material different from that of the first metal layer and that of the second metal layer. A plurality of cooling features are embedded in the material of the cooling layer. The cooling channels are spaced apart from both the first metal layer and the second metal layer by the material of the cooling layer. An electrically conductive path connects the first metal plate to the second metal plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.