Method for manufacturing a semiconductor structure using isolation layers for etching the trenches in a substrate
US12063769B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2021 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | Sep 6, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same. The manufacturing method includes: providing a substrate and bit line structures on the substrate; forming a first isolation layer, the first isolation layer being located on side walls of the bit line structures and on the substrate; forming a second isolation layer, the second isolation layer covering the first isolation layer located on the side walls of the bit line structures, and exposing the first isolation layer located on the substrate; removing the first isolation layer exposed by the second isolation layer and part of the first isolation layer below the second isolation layer, so that remaining of the first isolation layer is recessed compared to the second isolation layer toward the side walls of the bit line structures to form a groove.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.