Read only memory
US12063775B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 11, 2023 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | Oct 11, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/57
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.