Cache line demote infrastructure for multi-processor pipelines
US12066939B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2020 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Sep 20, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples described herein relate to a manner of demoting multiple cache lines to shared memory. In some examples, a shared cache is accessible by at least two processor cores and a region of the cache is larger than a cache line and is designated for demotion from the cache to the shared cache. In some examples, the cache line corresponds to a memory address in a region of memory. In some examples, an indication that the region of memory is associated with a cache line demote operation is provided in an indicator in a page table entry (PTE). In some examples, the indication that the region of memory is associated with a cache line demote operation is based on a command in an application executed by a processor. In some examples, the cache is an level 1 (L1) or level 2 (L2) cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.