Memory latency-aware GPU architecture
US12067642B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2020 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Sep 23, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One or more processing units, such as a graphics processing unit (GPU), execute an application. A resource manager selectively allocates a first memory portion or a second memory portion to the processing units based on memory access characteristics. The first memory portion has a first latency that is lower that a second latency of the second memory portion. In some cases, the memory access characteristics indicate a latency sensitivity. In some cases, hints included in corresponding program code are used to determine the memory access characteristics. The memory access characteristics can also be determined by monitoring memory access requests, measuring a cache miss rate or a row buffer miss rate for the monitored memory access requests, and determining the memory access characteristics based on the cache miss rate or the row buffer miss rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.