Memory circuits, memory structures, and methods for fabricating a memory device
US12068023B2 · kind B2 · utility
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12References
20Claims
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Key dates
| Filing date | Dec 8, 2021 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Oct 17, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory structure includes a first memory array having bit lines; a second memory array having bit lines; a first sense amplifier connected to a first bit line of the first memory array and a first bit line of the second memory array; and a second sense amplifier connected to a second bit line of the first memory array and a second bit line of the second memory array. The second bit line of the first memory array is adjacent to the first bit line of the first memory array, and the second bit line of the second memory array is adjacent to the first bit line of the second memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.