Circuitry for parallel set and reset of resistive random-access memory (ReRAM) cells
US12068028B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2022 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Jan 14, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive random-access memory (ReRAM) array with parallel reset and set programming and a method for programming is presented. The ReRAM array includes a plurality of ReRAM cells arranged in an array, wherein the array includes a plurality of rows and a plurality of columns, wherein at least two ReRAM cells of an array includes a word, wherein each ReRAM cell includes a select device having a control port, a first port, and a second port, and a resistive element; and a plurality of controllers, wherein the output of each of the plurality of controllers cause a reset programming or a set programming of the ReRAM cell in the column of the plurality of ReRAM cells that has the respective word line activated; such that the reset programming and the set programming occur in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.