Patent · US Active

Sacrificial pads to prevent galvanic corrosion of FLI bumps in EMIB packages

US12068172B2 · kind B2 · utility

0Cited by

2References

13Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Tarek A. Ibrahim · Mesa, US
Rahul N. Manepalli · Chandler, US
Wei-Lun Kane Jen · Chandler, US
Steve Cho · Chandler, US
Jason M. Gamba · Pasadena, US
Javier Soto Gonzalez · Chandler, US

Key dates

Filing date	Jul 30, 2019
Grant date	Aug 20, 2024
Priority date	—
Expiry date	Aug 18, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/19105
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Embodiments disclosed herein include electronic packages and methods of making electronic packages. In an embodiment, the electronic package comprises a package substrate, an array of first level interconnect (FLI) bumps on the package substrate, wherein each FLI bump comprises a surface finish, a first pad on the package substrate, wherein the first pad comprises the surface finish, and wherein a first FLI bump of the array of FLI bumps is electrically coupled to the first pad, and a second pad on the package substrate, wherein the second pad is electrically coupled to the first pad.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.