Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
US12068255B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2021 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Aug 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. The channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. A wall in the lowest conductive tier is aside the conducting material. The wall is in a region that is edge-of-plane relative to the memory plane. The edge-of-plane region comprises a TAV region. The wall is horizontally-elongated relative to an edge of the TAV region that is in the edge-of-plane region. Other memory arrays and methods are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.