Semiconductor package
US12068270B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 4, 2020 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Jun 20, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a redistribution substrate, and a semiconductor chip disposed on a top surface of the redistribution substrate. The redistribution substrate includes under bump patterns laterally spaced apart from each other, a dummy pattern disposed between the under bump patterns, a passivation pattern disposed on a bottom surface of the dummy pattern, an insulating layer covering top surfaces and sidewalls of the under bump patterns and a sidewall and a top surface of the dummy pattern, and a redistribution pattern disposed on one of the under bump patterns and electrically connected to the one under bump pattern. The passivation pattern includes a different material from that of the insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.