Integrated circuit structure with avalanche junction to doped semiconductor over semiconductor well

US12068308B2 · kind B2 · utility

Assignee

• GLOBALFOUNDRIES U.S. Inc. · US

Inventors

• Robert J. Gauthier, JR. · Williston, US
• Alain Loiseau · Williston, US
• Souvick Mitra · South Burlington, US
• Tsung-Che Tsai · Hsinchu, TW
• Meng Miao · Williston, US
• You Li · South Burlington, US

Key dates

• Filing date: Jun 24, 2022
• Grant date: Aug 20, 2024
• Expiry date: Dec 21, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/611

Abstract

Embodiments of the disclosure provide an integrated circuit (IC) structure, including a triple well structure within a semiconductor substrate. A base region is within a doped well of the triple well structure, a collector terminal is within the doped well and laterally separated from the base region by a first insulator and a first avalanche junction is defined between a first pair of oppositely-doped semiconductor regions within the collector terminal. An emitter terminal is within the third doped well of the triple well structure and laterally separated from the collector terminal by a second insulator. A second avalanche junction is defined between a second pair of oppositely-doped semiconductor regions of the emitter terminal.