Fin field-effect transistor with void and method of forming the same
US12068398B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2023 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Apr 25, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.