Memory device, method for configuring memory cell in N-bit memory unit, and memory array
US12069970B2 · kind B2 · utility
0Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2022 |
| Grant date | Aug 20, 2024 |
| Priority date | — |
| Expiry date | Jun 18, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure provides a memory device, a method for configuring a first memory cell in an N-bit memory unit of a memory array, and a memory array. The memory device includes a memory array including an N-bit memory unit, wherein N is a positive integer. The N-bit memory unit includes a first memory cell, used to characterize at least two first bits of a plurality of least significant bits of the N-bit memory unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.