Debug state machine triggered extended performance monitor counter
US12072378B2 · kind B2 · utility
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4References
20Claims
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Key dates
| Filing date | Dec 9, 2019 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Apr 26, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3698
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) includes a debug controller, a debug state machine (DSM), and an extended performance monitor counter (EPMC). The debug controller that selectively outputs debug data on a debug interconnect. The DSM identifies an event based on the debug data and an event list and outputs a DSM indication that identifies the event. The EPMC indicates a plurality of detected events including the identified event. The EPMC indicates the identified event in response to the DSM indication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.