High capacity memory circuit with low effective latency
US12073082B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2023 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Apr 24, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1435
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.