Stacked command queue
US12073114B2 · kind B2 · utility
0Cited by
7References
21Claims
0Family size
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Key dates
| Filing date | Sep 30, 2021 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Feb 10, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller includes a command queue with multiple entry stacks, each with a plurality of entries holding memory access commands, one or more parameter indicators each holding a respective characteristic common to the plurality of entries, and a head indicator designating a current entry for arbitration. An arbiter has a single command input for each entry stack. A command queue loader circuit receives incoming memory access commands and loads entries of respective entry stacks with memory access commands having the respective characteristic of each of the one or more parameter indicators in common.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.