Receiver with pipeline structure for receiving multi-level signal and memory device including the same
US12073875B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2022 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Feb 14, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/101
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A receiver receiving a multi-level signal includes a sample and hold circuit, first and second analog-to-digital converting circuits, and a digital-to-analog converting circuit. The sample and hold circuit generates a sample data signal by sampling and holding an input data signal. The first analog-to-digital converting circuit generates a first bit of output data based on the input data signal and a first selection reference voltage among a plurality of reference voltages. The digital-to-analog converting circuit selects at least one additional selection reference voltage from among the plurality of reference voltages based on the first bit of the output data. The second analog-to-digital converting circuit generates at least one additional bit of the output data based on the sample data signal and the at least one additional selection reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.