Memory device that includes a duty correction circuit, memory controller that includes a duty sensing circuit, and storage device that includes a memory device
US12073917B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2021 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Jul 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage device includes a plurality of memory chips and a chip. The plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal, and a second memory chip configured to generate a second signal based on a second clock signal. The chip is configured to receive the first and second signals and generate and output a first and second comparison signal based on a duty cycle of the first and second signals. The first memory chip is further configured to generate a first corrected signal by adjusting a duty cycle of the first clock signal based on the first comparison signal, and the second memory chip is further configured to generate a second corrected signal by adjusting a duty cycle of the second clock signal based on the second comparison signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.