Fail-safe protection architecture for high voltage tolerant input/output circuit
US12074597B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2022 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Dec 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00384
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit provides fail safe protection of an input/output (I/O) circuit of a chip. The I/O circuit comprises an I/O pad connected to one or more other chips via an I/O bus. The circuit comprise a supply and failsafe detector component. The supply and failsafe detector component generates an I/O supply output signal. The I/O supply output signal has a low voltage value when the I/O supply voltage of the chip is below a medium voltage level and the I/O supply output signal having a high voltage value when the I/O supply voltage of the chip is above the medium voltage level. The medium voltage is above a threshold voltage of the transistor of the I/O circuit and below the high voltage value. The circuit uses the I/O supply output signal to provide a reference voltage as input to the transistor of the I/O circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.