Semiconductor memory device
US12075611B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2021 |
| Grant date | Aug 27, 2024 |
| Priority date | — |
| Expiry date | Apr 23, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory includes a bit line extending in a first direction, first and second active patterns, which are alternately disposed in the first direction and on the bit line, and each of which includes a horizontal portion and a vertical portion, first word lines disposed on the horizontal portions of the first active patterns to cross the bit line, second word lines disposed on the horizontal portions of the second active patterns to cross the bit line, and an intermediate structure provided in a first gap region between the first and second word lines or in a second gap region between the vertical portions of the first and second active patterns. The first and second active patterns, which are adjacent to each other, may be disposed to be symmetric with respect to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.