Command address fault detection
US12079078B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2022 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Sep 28, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/079
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Implementations described herein relate to command address fault detection. A memory device may receive, from a host device via a command address (CA) bus, a plurality of CA bits associated with a command signal or an address signal. The memory device may receive, from the host device via the CA bus, a first set of parity bits that is based on the plurality of CA bits and a select parity generation process. The memory device may generate a second set of parity bits, based on the plurality of CA bits, using the select parity generation process. The memory device may compare the first set of parity bits and the second set of parity bits. The memory device may selectively transmit an alert signal to the host device based on comparing the first set of parity bits and the second set of parity bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.