Efficient dual-path floating-point arithmetic operators
US12079590B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2020 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Jan 2, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods related to performing arithmetic operations on floating-point numbers. Floating-point arithmetic circuitry is configured to receive two floating-point numbers. The floating-point arithmetic circuitry includes a first path configured to perform a first operation on the two floating-point numbers based at least in part on a difference in size between the two floating-point numbers. The floating-point arithmetic circuitry includes a second path configured to perform a second operation on the two floating-point numbers based at least in part on the difference is size between the two floating-point numbers. The first path and the second path diverge from each other after receipt of the floating-point numbers in the floating-point arithmetic circuitry and converge on a shared adder that is used for the first operation and the second operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.