Power saving floating point Multiplier-Accumulator with a high precision accumulation detection mode
US12079593B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 21, 2021 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Dec 15, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/4876
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating point multiplier-accumulator (MAC) multiplies and accumulates N pairs of floating point values using N MAC processors operating simultaneously, each pair of values comprising an input value and a coefficient value to be multiplied and accumulated. The pairs of floating point values are simultaneously processed by the plurality of MAC processors, each of which output a signed integer form fraction with a first bitwidth and a second bitwidth, along with a maximum exponent. The first bitwidth signed integer form fractions are summed by an adder tree using the first bitwidth to form a first sum, and when an excess leading 0 condition is detected, a second adder tree operative on the second bitwidth integer form fractions forms a second sum. The first sum or second sum, along with the maximum exponent, is converted into floating point result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.