Circuits and methods of detecting at least partial breakdown of canary circuits
US12080378B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2022 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Jun 18, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one implementation of the present disclosure, a circuit comprises: a memory array comprising one or more groupings of bitcells, one or more bitlines, and one or more wordlines; and one or more canary circuits coupled to the memory array, wherein each of the canary circuits is configured to predict at least partial breakdown of a corresponding grouping of bitcells in the memory array. According to one implementation of the present disclosure, a method includes: providing an excitation stress on one or more canary circuits corresponding to a grouping of bitcells in a memory array; detecting at least a partial breakdown of the one or more canary circuits; and generating a flag.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.