Semiconductor device
US12080379B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2022 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Mar 2, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device according to an embodiment includes a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of a plurality of divided clock signals. A calibration circuit applies a first offset clock signal to a first sampler circuit, applies a second offset clock signal having an opposite phase to the first offset clock signal to a second sampler circuit, and generates a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.