Semiconductor manufacturing method
US12080606B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2021 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Mar 9, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present application provides a method for manufacturing a semiconductor, comprising providing a substrate, on which a first, second and third dielectric layers are successively formed, the third dielectric layer having an initial opening; forming a first deposited layer which at least covers a side wall of the initial opening to form a first mask layer having a first opening; removing the second dielectric layer directly below the first opening to expose a side wall of the second dielectric layer; forming a second deposited layer which at least covers the side wall of the first opening and the exposed side wall of the second dielectric layer, to form a second mask layer having a second opening; removing the first dielectric layer directly below the second opening to expose the substrate; and removing the second mask layer, and forming a trench by etching the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.