Patent · US Active

Method to implement wafer-level chip-scale packages with grounded conformal shield

US12080655B2 · kind B2 · utility

1Cited by

3References

22Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Gianni SIGNORINI · Garching bei München, DE
Georg Seidemann · Landshut, DE
Bernd Waidhas · Nittendorf, DE

Key dates

Filing date	Mar 28, 2019
Grant date	Sep 3, 2024
Priority date	—
Expiry date	May 21, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/00014
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Embodiments disclosed herein include electronic packages with conformal shields and methods of forming such packages. In an embodiment, the electronic package comprises a die having a first surface, a second surface opposite the first surface, and sidewall surfaces. A redistribution layer is over the first surface of the die, and the redistribution layer comprises a first conductive layer. In an embodiment, an under ball metallization (UBM) layer is over the redistribution layer, and a conductive shield is over the sidewall surfaces of the die and the second surface of the die. In an embodiment, the conductive shield is electrically coupled to the UBM layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.