Semiconductor memory device and method for fabricating the same
US12080791B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2021 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Dec 31, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.