Semiconductor structure and forming method therefor, and memory and forming method therefor
US12082419B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2021 |
| Grant date | Sep 3, 2024 |
| Priority date | — |
| Expiry date | Sep 20, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/63
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for forming the semiconductor structure includes: providing a substrate, forming a sacrificial layer and an active layer on the sacrificial layer on the substrate; etching the active layer and the sacrificial layer to form active lines extending along a first direction; forming a first isolation layer that fills a spacing between the active lines; etching ends of the active lines to form openings, and exposing the sacrificial layer on side walls of the openings; removing the sacrificial layer along the openings, and forming gap between a bottom of the active lines and the substrate; and filling the gaps with a conductive material to form bit lines extending along the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.