Low etch pit density 6 inch semi-insulating gallium arsenide wafers
US12084790B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2023 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Jun 20, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/50
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm−2, and a resistivity of 1×107 Ω-cm or more. The wafer may have an optical absorption of less than 5 cm−1 less than 4 cm−1 or less than 3 cm−1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm2/V-sec or higher. The wafer may have a thickness of 500 μm or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1×107 cm−3 or less.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.