Systems and methods for reducing instruction code memory footprint for multiple processes executed at a coprocessor
US12086447B2 · kind B2 · utility
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2References
15Claims
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Key dates
| Filing date | Dec 18, 2019 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Feb 22, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes a first processor couplable to a first memory and a second memory. In response to a page migration trigger for a page in the first memory, the first processor is configured to, responsive to the page being a read-only page storing code for execution, initiate migration of the page to a code cache portion of a second memory associated with a second processor and shared by multiple processes executing at the second processor, and to configure each process of a set of processes executing at the second processor to access and execute the code from the code cache portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.