Patent · US Active

Circuit design modification using timing-based yield calculation

US12086529B1 · kind B1 · utility

0Cited by

3References

20Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Igor Keller · Pleasanton, US
Eric Anderson · Grafton, US
Yang Gao · Hangzhou City, CN

Key dates

Filing date	Mar 10, 2022
Grant date	Sep 10, 2024
Priority date	—
Expiry date	May 2, 2043

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various embodiments provide for using a timing-based yield calculation to modify a circuit design, which can be part of an electronic design automation (EDA) system. For instance, some embodiments use a timing-based yield calculation to modify one or more portions of the circuit design to improve timing of the circuit design (e.g., slack, slew, delay, etc.), the timing-based yield calculation of the circuit design, or both.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.