Device, method and system to predict an address collision by a load and a store
US12086591B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2021 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Oct 19, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3856
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques and mechanisms for determining a relative order in which a load instruction and a store instruction are to be executed. In an embodiment, a processor detects an address collision event wherein two instructions, corresponding to different respective instruction pointer values, target the same memory address. Based on the address collision event, the processor identifies respective instruction types of the two instructions as an aliasing instruction type pair. The processor further determines a count of decisions each to forego a reversal of an order of execution of instructions. Each decision represented in the count is based on instructions which are each of a different respective instruction type of the aliasing instruction type pair. In another embodiment, the processor determines, based on the count of decisions, whether a later load instruction is to be advanced in an order of instruction execution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.