Processing sequential inputs using neural network accelerators
US12086706B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2019 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Dec 19, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware accelerator can store, in multiple memory storage areas in one or more memories on the accelerator, input data for each processing time step of multiple processing time steps for processing sequential inputs to a machine learning model. For each processing time step, the following is performed. The accelerator can access a current value of a counter stored in a register within the accelerator to identify the processing time step. The accelerator can determine, based on the current value of the counter, one or more memory storage areas that store the input data for the processing time step. The accelerator can facilitate access of the input data for the processing time step from the one or more memory storage areas to at least one processor coupled to the one or more memory storage areas. The accelerator can increment the current value of the counter stored in the register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.