Modulation of source voltage in NAND-flash array read
US12087365B2 · kind B2 · utility
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Key dates
| Filing date | Mar 15, 2021 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Dec 14, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Modulation of the source voltage in a NAND-flash array read waveform can enable improved read-disturb mitigation. For example, increasing the source line voltage to a voltage with a magnitude greater than the non-idle source voltage during the read operation when the array is idle (e.g., not during sensing) enables a reduction in read disturb without the complexity arising from the consideration of multiple read types. Additional improvement in FN disturb may also be obtained on the sub-blocks in the selected SGS by increasing the source line voltage during the selected wordline ramp when the array is idle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.