Intel NDTM US LLC
25Patents
25Active
25Granted
54Portfolio score
Filing activity: Mar 24, 2020 → Apr 30, 2024
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US12046303B2 | Smart prologue for nonvolatile memory program operation | Physics | 0 | Active |
| US12360669B2 | Method and apparatus to reduce memory in a NAND flash device to store page related information | Physics | 0 | Active |
| US12322455B2 | Program verify process having placement aware pre-program verify (PPV) bucket size modulation | Physics | 0 | Active |
| US12131785B2 | Weak erase pulse | Physics | 0 | Active |
| US12089412B2 | Vertical string driver with extended gate junction structure | Electricity | 0 | Active |
| US12254933B2 | Smart prologue for nonvolatile memory program operation | Physics | 0 | Active |
| US12230334B2 | Dynamic program caching | Physics | 0 | Active |
| US12087365B2 | Modulation of source voltage in NAND-flash array read | Physics | 0 | Active |
| US12362002B2 | Staggered read recovery for improved read window budget in a three dimensional (3D) NAND memory array | Physics | 0 | Active |
| US12432922B2 | Method and apparatus to mitigate word line staircase etch stop layer thickness variations in 3D NAND devices | Electricity | 0 | Active |
| US12362016B2 | Read latency reduction for partially-programmed block of non-volatile memory | Physics | 0 | Active |
| US12315567B2 | Grouped global wordline driver with shared bias scheme | Physics | 0 | Active |
| US12237023B2 | Dynamic detection and dynamic adjustment of sub-threshold swing in a memory cell sensing circuit | Physics | 0 | Active |
| US12266406B2 | NAND sensing circuit and technique for read-disturb mitigation | Physics | 0 | Active |
| US12051469B2 | Method and apparatus to mitigate hot electron read disturbs in 3D nand devices | Physics | 0 | Active |
| US12148802B2 | Vertical string driver with channel field management structure | Electricity | 0 | Active |
| US12424483B2 | 3D NAND with inter-wordline airgap | Electricity | 0 | Active |
| US12094545B2 | Techniques for preventing read disturb in NAND memory | Physics | 0 | Active |
| US12315573B2 | Method and apparatus to reduce power consumption of page buffer circuitry in a non-volatile memory device | Physics | 0 | Active |
| US12379989B2 | Zero voltage program state detection | Physics | 0 | Active |
| US11923010B2 | Flash memory chip that modulates its program step voltage as a function of chip temperature | Physics | 0 | Active |
| US12394497B2 | Efficient bitline stabilization for program inhibit in NAND arrays | Physics | 0 | Active |
| US12394492B2 | Memory cell sensing circuit with adjusted bias from pre-boost operation | Physics | 0 | Active |
| US12189955B2 | Skip program verify for dynamic start voltage sampling | Physics | 0 | Active |
| US12393367B2 | Lean command sequence for multi-plane read operations | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.