Virtualized scan chain testing in a random access memory (RAM) array
US12087383B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2022 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Jul 1, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Virtualized scan chain testing in a random access memory array, and related methods and computer-readable media are disclosed. To facilitate virtualized scan chain testing, the memory array includes an integrated test circuit that causes the memory array to behave as a serialized scan chain. The integrated test circuit forces serialized write and read access to offset entries in the memory array on each scan cycle in a scan mode based on received serialized test data. After the number of scan cycles equals the number of entries the memory array, the entries in the memory array are fully initialized with test data from the serial test data flow. In subsequent scan cycles, the integrated test circuit continues to perform serial read operations to cause stored serial test data to be serially shifted out as an output serial data flow that then be compared to the original serial test data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.