Method of performing internal processing operations with pre-defined protocol interface of memory device
US12087388B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2021 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | Oct 19, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.