Patent · US Active

Method of making an individualization zone of an integrated circuit

US12087707B2 · kind B2 · utility

1Cited by

0References

11Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Nicolas Posseme · Grenoble, FR
Stefan Landis · Tullins, FR

Key dates

Filing date	Jul 21, 2021
Grant date	Sep 10, 2024
Priority date	—
Expiry date	Aug 18, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/76808
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method for making an individualization zone of a microchip comprising a first level and a second level of electrical tracks, and a level of interconnections comprising vias. The method includes: providing the first level and a dielectric layer, making a hard metal mask on the dielectric layer, etching the dielectric layer through the mask openings by etching based on fluorinated chemistry, preferably oxidizing the hard metal mask by hydrolysis so as to form randomly distributed residues at certain openings, and filling the openings so as to form at least the vias of the level of interconnections, the vias comprising functional vias at the openings without residues and inactive vias at the openings with residues.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.