Gate structures in transistor devices and methods of forming same
US12087775B2 · kind B2 · utility
0Cited by
11References
20Claims
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Key dates
| Filing date | Sep 1, 2021 |
| Grant date | Sep 10, 2024 |
| Priority date | — |
| Expiry date | May 26, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes first transistor having a first gate stack and first source/drain regions on opposing sides of the first gate stack; a second transistor having a second gate stack and second source/drain regions on opposing sides of the second gate stack; and a gate isolation structure separating the first gate stack from the second gate stack. The gate isolation structure includes a dielectric liner having a varied thickness along sidewalls of the first gate stack and the second gate stack and a dielectric fill material over the dielectric liner, wherein the dielectric fill material comprises a seam.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.