Self-aligned front-end charge trap flash memory cell and capacitor design for integrated high-density scaled devices

US12089411B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Tanuj Trivedi · Hillsboro, US
• Walid M. Hafez · Portland, US
• Rohan K. Bambery · Hillsboro, US
• Daniel B. O'Brien · Beaverton, US
• Christopher Alan Nolph · Hillsboro, US
• Rahul Ramaswamy · Portland, US
• Ting Chang · Portland, US

Key dates

• Filing date: Jun 23, 2020
• Grant date: Sep 10, 2024
• Expiry date: Jan 11, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/834

Abstract

Embodiments disclosed herein include a semiconductor device and methods of forming such a device. In an embodiment, the semiconductor device comprises a substrate and a transistor on the substrate. In an embodiment, the transistor comprises a first gate electrode, where the first gate electrode is part of a first array of gate electrodes with a first pitch. In an embodiment, the first gate electrode has a first average grain size. In an embodiment, the semiconductor device further comprises a component cell on the substrate. In an embodiment, the component cell comprises a second gate electrode, where the second gate electrode is part of a second array of gate electrodes with a second pitch that is larger than the first pitch. In an embodiment, the second gate electrode has a second average grain size that is larger than the first average grain size.