Hardware accelerator
US12093531B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2021 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | May 3, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06V10/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware accelerator is provided. The hardware accelerator includes a first memory; a source address generation unit coupled to the first memory; a data collection unit coupled to the first memory; a first data queue coupled to the data collection unit; a data dispersion unit coupled to the first data queue; a destination address generation unit coupled to the data dispersion unit; an address queue coupled to the destination address generation unit; a second data queue coupled to the data dispersion unit; and a second memory coupled to the second data queue. The hardware accelerator can perform anyone or any combination of tensor stride, tensor reshape and tensor transpose to achieve tensorflow depth-to-space permutation or tensorflow space-to-depth permutation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.