Memory system and operating method of memory system
US12093554B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2022 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Feb 17, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. In one aspect, a memory system is provided to comprise a memory device including a plurality of memory dies, each memory die including a plurality of memory blocks for storing data and different groups of memory blocks form one or more super blocks; and a memory controller in communication with the memory device and configured to count the number of super blocks in an erase state included in each memory die to identify a first memory die having the smallest number of super blocks in the erase state and a second memory die having the largest number of super blocks in the erase state, and move data stored in a first super block included in the first memory die to a second super block included in the second memory die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.