Method and apparatus for intensifying current leakage between adjacent memory cells, and method and apparatus for current leakage detection
US12094516B2 · kind B2 · utility
0Cited by
16References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2022 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Dec 13, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for intensifying current leakage between adjacent memory cells includes that: a write operation is performed on a memory array, to form a column strip test pattern, the column strip test pattern being formed by arranging low-level memory cells and high-level memory cells in columns, and N columns of high-level memory cells being present between two adjacent columns of low-level memory cells, N≥2; and voltage adjustment is performed on the low-level memory cells and the high-level memory cells, to increase potential differences between the low-level memory cells and the high-level memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.