Memory device, failure bits detector and failure bits detection method thereof
US12094554B2 · kind B2 · utility
0Cited by
2References
19Claims
0Family size
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Key dates
| Filing date | Oct 5, 2022 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Jan 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A memory device, a failure bits detector, and a failure bits detection method thereof are provided. The failure bits detector includes a current generator, a current mirror, and a comparator. The current generator generates a first current according to a reference code. The current mirror mirrors the first current to generate a second current at a second end of the current mirror. The comparator compares a first voltage at a first input end with a second voltage at a second input end to generate a detection result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.