Semiconductor arrangement comprising isolation structure comprising at least two electrical insulator layers
US12094756B2 · kind B2 · utility
0Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Jul 27, 2022 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Jul 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor arrangement includes an isolation structure having a first electrical insulator layer in a trench in a semiconductor substrate and a second electrical insulator layer in the trench and over the first electrical insulator layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.