Power semiconductor device with free-floating packaging concept
US12094791B2 · kind B2 · utility
0Cited by
5References
21Claims
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Key dates
| Filing date | Oct 10, 2019 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | Jan 9, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/08245
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power semiconductor device includes a semiconductor wafer having a junction and a junction termination laterally surrounding the junction. A protection layer covers the lateral side of the semiconductor wafer and covers the second main side at least in an area of the junction termination. A first metal disk is arranged on the first main side to cover the first main side of the semiconductor wafer. An interface between the first metal disk and the semiconductor wafer is a free floating interface. A metal layer sandwiched between the first metal disk and the semiconductor wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.