Semiconductor package and method of manufacturing the same
US12094847B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2021 |
| Grant date | Sep 17, 2024 |
| Priority date | — |
| Expiry date | May 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package may include: a first redistribution substrate; a first die above the first redistribution substrate; a second redistribution substrate on the first die; a first bump formed on the first die, and connecting the first die to the second redistribution substrate; a first molding portion enclosing the first die and surrounding the first bump; and an outer terminal on a bottom surface of the first redistribution substrate, wherein the second redistribution substrate comprises an insulating pattern and a conductive pattern in the insulating pattern to be in contact with the first bump, and wherein, at an interface of the second redistribution substrate and the first bump, the conductive pattern of the second redistribution substrate and the first bump are formed of the same material to form a single body or structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.